1. Field of the Invention
The present invention relates to a stackable semiconductor package, and more particularly, to a stackable semiconductor package having at least two chips.
2. Description of the Related Art
FIG. 1 is a schematic sectional view of a conventional stackable semiconductor package. The conventional stackable semiconductor package 1 includes a first substrate 11, a chip 12, a second substrate 13, a plurality of wires 14 and a molding compound 15. The first substrate 11 has a first surface 111 and a second surface 112. The chip 12 is attached to the first surface 111 of the first substrate 11 by flip-chip bonding. The second substrate 13 is adhered to the chip 12 with an adhesive layer 16. The second substrate 13 has a first surface 131 and a second surface 132, and the first surface 131 has a plurality of first pads 133 and a plurality of second pads 134 thereon. From the top view, the area of the second substrate 13 is greater than the area of the chip 12, such that some parts of the second substrate 13 extend out of the chip to form an overhanging portion.
The wires 14 electrically connect the first pads 133 of the second substrate 13 and the first surface 111 of the first substrate 11. The molding compound 15 encapsulates the first surface 111 of the first substrate 11, the chip 12, the wires 14, and a part of the second substrate 13, and exposes the second pads 134 on the first surface 131 of the second substrate 13, so as to form a mold area opening 17. Usually, the conventional stackable semiconductor package 1 can have another package 18 or other elements stacked in the mold area opening 17, in which solder balls 181 of the package 18 are electrically connected to the second pads 134 of the second substrate 13.
The conventional stackable semiconductor package 1 usually includes one chip only (i.e., the chip 12), so the application thereof is limited. Moreover, as the second substrate 13 has an overhanging portion, the first pads 133 are located on the periphery (i.e., the overhanging portion) of the corresponding position of the chip 12. The distance between the first pads 133 and the corresponding position of the edge of the chip 12 is defined as an overhanging length L1. Experiments show that if the overhanging length L1 is greater than three times the thickness T1 of the second substrate 13, the overhanging portion will sway or vibrate in wire bonding, which is disadvantageous to the wire bonding. Furthermore, during the wire bonding, the second substrate 13 may crack under a severe downward stress. Furthermore, due to the aforementioned sway, vibration or crack, the overhanging portion cannot be too long, such that the area of the second substrate 13 is limited and the layout space of the second pads 134 on the first surface 131 of the second substrate 13 is exposed by the mold area opening 17.
Therefore, it is necessary to provide a stackable semiconductor package to solve the above problems.